Field-Programmable Gate Array (FPGA)

A Field-Programmable Gate Array (FPGA) is an integrated circuit that uses a combination of programmable logic lookup tables, arithmetic logic units optimized for digital signal processing, and a matrix of memory cells to define how all of these elements are connected.

Context:
- It can be specified using a Hardware Description Language (HDL).
- …
Example(s):
- a Altera Stratix FPGA.
- a Xilinx Virtex-7.
- …
Counter-Example(s):
- a Graphics Processing Unit (GPU), such as Nvidea GeForce chip.
See: Flip-Flop (Electronics), Integrated Circuit, Field-Programmable, Hardware Description Language, Application-Specific Integrated Circuit, Circuit Diagram, Programmable Logic Device, Logic Block, Combinational Logic, Logic Gate, AND Gate, XOR Gate.

References

(Wikipedia, 2018) ⇒ https://en.wikipedia.org/wiki/Field-programmable_gate_array Retrieved:2018-3-19.
- A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing - hence “field-programmable”. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare.)
  FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

(Zhang et al., 2015) ⇒ Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, and Jason Cong. (2015). “Optimizing Fpga-based Accelerator Design for Deep Convolutional Neural Networks.” In: Proceedings of the 2015 ACM / SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161-170 . ACM,

http://cacm.acm.org/magazines/2015/7/188737-growing-pains-for-deep-learning/fulltext
- QUOTE: although individual GPUs provide peak floating-point performance, in the deep neural network applications used by Baidu, the FPGA consumes less power for the same level of performance and could be mounted on a server blade, powered solely from the PCI Express bus connections available on the motherboard. A key advantage of the FPGA is that because the results from one calculation can be fed directly to the next without needing to be held temporarily in main memory, the memory bandwidth requirement is far lower than with GPU or CPU implementations.